There is a moment in every discrete amplifier design when the schematic is complete, the component values look reasonable, and the Bode plot is finally on the screen. For many designers that moment is also when the phase characteristic, scrolling downward through 90 degrees, then 135, then accelerating toward 180, delivers an uncomfortable message. The open-loop phase reaches 180 degrees before the gain has fallen to unity. The amplifier is unstable. What the designer holds in that moment is not a failed schematic. It is a feedback system that needs a dominant pole, and the tool for creating it is the Miller capacitor.
Selecting its value correctly requires reading the logarithmic phase diagram not as a graphical curiosity but as a precise instruction. Every feature of that curve, where the slope steepens, where it levels off, where it approaches 180 degrees, maps directly to a circuit element. Understanding that correspondence is what converts the phase diagram from a verdict into a procedure.
Why the Uncompensated VAS Is Unstable
The voltage amplification stage of a discrete amplifier is a high-gain inverting stage, typically a common-emitter or common-source transistor loaded by a current source. At DC the stage contributes gain of A₀ = gm · R_out, where gm is the transconductance of the VAS transistor and R_out is the parallel combination of the transistor's output resistance ro and the output resistance of the current source load. For a well-biased BJT operating at a collector current of 1 mA, gm = IC / VT ≈ 1mA / 26mV ≈ 38 mA/V. With R_out of several hundred kilohms, A₀ can reach 60 to 80 dB.
Such a high-gain stage has at least two significant poles in its open-loop transfer function. The first arises from the RC time constant at the VAS transistor's collector node, formed by R_out and the total capacitance C₁ loading that node, including transistor parasitic capacitances and any stray wiring capacitance. The second pole arises from the output node of the amplifier, formed by the output stage impedance and the load. For a two-pole system the open-loop transfer function takes the form:
A(s) = A₀ / [(1 + s/ω_p1) · (1 + s/ω_p2)]
At frequencies above both poles, this function contributes 180 degrees of phase lag from the poles alone, which is added to the inherent 180-degree phase inversion of negative feedback. The total phase shift at the unity-gain frequency exceeds 360 degrees, and the system oscillates. The Bode phase plot shows this graphically: two successive 45-degree-per-decade transitions merge into a slope that sweeps through 180 degrees before the gain curve has reached 0 dB. The phase margin, defined as φm = 180° + arg[A(jωc) · F(jωc)] where ωc is the unity-gain crossover frequency, is zero or negative.
What the Miller Capacitor Does to the Pole Locations
Adding a capacitor Cc between the output and input of the VAS (across the inverting gain stage) introduces feedback local to that stage. The Miller effect transforms Cc into an equivalent input capacitance of C_M = Cc · (1 + |A_VAS|), where A_VAS is the voltage gain of the VAS transistor. If A_VAS = 500, a 10 pF capacitor appears as 5 nF at the input node of the VAS, dramatically lowering the first pole frequency.
The result is pole splitting. The first pole ω_p1 moves to a lower frequency, approximately:
ω_p1(new) ≈ 1 / (R_out · Cc · |A_VAS|) = gm2 / (Cc · A₀)
while the second pole ω_p2 moves to a higher frequency:
ω_p2(new) ≈ gm2 / (C₂ + Cc)
where gm2 is the transconductance of the VAS transistor and C₂ is the total capacitance at the output node. The two poles have been pushed apart. If Cc is large enough, ω_p1(new) is so low that the gain curve falls below 0 dB before ω_p2(new) is reached. The amplifier behaves as a single-pole system over the range of interest, and the phase at the unity-gain crossover frequency is dominated by the first pole alone, leaving a margin approaching 90 degrees in the ideal case.
The gain-bandwidth product of the compensated stage is fixed by gm and Cc:
GBW = gm / (2π · Cc)
This is the central design equation for Miller compensation. Once the tail current of the input differential pair (and thus gm) is chosen, the GBW is inversely proportional to Cc. A larger Cc buys stability at the cost of bandwidth. A smaller Cc preserves bandwidth but requires that the second pole ω_p2(new) is safely beyond the unity-gain frequency, which imposes a constraint on the minimum value of Cc.
Reading the Bode Phase Plot to Find the Minimum Safe Cc
The logarithmic phase characteristic of the uncompensated amplifier is the document that specifies what Cc must do. Consider a practical two-stage discrete amplifier with the following parameters extracted from the uncompensated Bode plot: first pole at f_p1 = 200 kHz, second pole at f_p2 = 3 MHz, DC gain A₀ = 80 dB = 10000. The unity-gain frequency without compensation would fall at approximately f_p1 · A₀ = 200 kHz · 10000 = 2 GHz, well above f_p2, so the phase at unity gain approaches 180 degrees and the system is unstable.
The design goal is a phase margin φm ≥ 45°. At the compensated unity-gain frequency f_c, the phase contributed by the second pole must not consume more than 180° − 90° − 45° = 45° of the phase budget, since the first pole alone contributes 90° asymptotically and the 45° margin must remain. The phase contributed by a single pole at frequency f_p is:
φ_pole = −arctan(f_c / f_p)
For this phase to be no more than 45°, it is required that arctan(f_c / f_p2(new)) ≤ 45°, which gives f_c ≤ f_p2(new). In words: the unity-gain crossover frequency must not exceed the second pole frequency after compensation. This is the fundamental stability criterion for a two-pole system with Miller compensation: the phase margin equals 90° − arctan(f_c / f_p2(new)), and reaching 45° requires placing f_c at or below f_p2(new).
From GBW = gm / (2π · Cc) and the requirement f_c = GBW / A_CL ≤ f_p2(new), the minimum Miller capacitor value needed to satisfy the 45° phase margin condition is:
Cc(min) = gm / (2π · A_CL · f_p2(new))
where A_CL is the closed-loop gain. For the example above, with gm = 38 mA/V, A_CL = 20 (26 dB), and f_p2(new) ≈ 3 MHz after compensated pole splitting:
Cc(min) = 0.038 / (2π · 20 · 3 × 10⁶) ≈ 101 pF
In practice, component tolerances and parasitic capacitances add to the effective second-pole capacitance, so the computed Cc should be increased by 20 to 30 percent. A starting value of 120 pF to 150 pF is appropriate for this example. The actual value is then trimmed by examining the phase margin on the Bode plot and observing the step response: a well-compensated amplifier shows a clean step response with 10 to 30 percent overshoot at φm = 45° and near-critical damping at φm = 65°.
The Right-Half-Plane Zero and Why It Corrupts the Phase Budget
A plain Miller capacitor creates an unintended hazard. Because Cc provides a signal path from the input of the VAS directly to its output, bypassing the transistor entirely at high frequencies, there exists a frequency at which the forward signal through Cc and the signal through the transistor are equal in magnitude and opposite in phase. This is the right-half-plane zero (RHP zero), located at:
f_z = gm2 / (2π · Cc)
The RHP zero adds phase lag, not lead, making it doubly destructive: it coincides with the GBW frequency, which means it appears precisely at the critical crossover point on the Bode diagram. Its phase contribution is −arctan(f_c / f_z), adding to the phase lag already present from the poles and eroding the margin that the pole splitting was intended to create. For the example values, f_z = 0.038 / (2π · 120 × 10⁻¹²) ≈ 50 MHz, well above the unity-gain frequency, so the RHP zero is benign in this case. But in amplifiers with lower gm or larger required Cc values, f_z can fall within a factor of three of f_c, consuming 15 to 20 degrees of phase margin and pushing a nominally stable design toward the margin limit.
The standard remedy is a nulling resistor Rz placed in series with Cc. With Rz present, the zero frequency becomes:
f_z(Rz) = 1 / [2π · Cc · (1/gm2 − Rz)]
Setting Rz = 1/gm2 moves the zero to infinity, eliminating its phase contribution entirely. Setting Rz > 1/gm2 moves the zero into the left half of the s-plane, where it becomes a phase-lead element that adds positive phase near the crossover frequency and can extend the phase margin by 15 to 25 degrees without changing the crossover frequency itself. For a VAS transistor biased at 1 mA, 1/gm ≈ 26 ohms, so a nulling resistor of 30 to 50 ohms in series with Cc is sufficient to neutralize or exploit the zero. In discrete designs this is conveniently realized as a small carbon film resistor whose value is trimmed during characterization.
Mapping the Phase Diagram to the Selection Procedure
The logarithmic phase characteristic is the practical tool that connects the theoretical criteria to a physical capacitor value. The procedure runs as follows.
First, measure or simulate the uncompensated open-loop Bode plot of the amplifier. Identify the frequency at which the phase first reaches −135 degrees. Call this f_135. The reciprocal of the slope of the phase curve at that point indicates whether the system has two closely spaced poles or well-separated ones. A steep slope through −135° signals closely spaced poles and a difficult compensation problem; a gradual slope signals well-separated poles and an easier one.
Second, identify the second pole frequency f_p2 from the inflection in the phase curve, where the phase slope changes from −20 dB/decade equivalent to −40 dB/decade equivalent. This frequency sets the ceiling for the compensated unity-gain crossover: f_c must remain below f_p2 for a 45° margin, and below f_p2 / √3 ≈ 0.577 · f_p2 for a 60° margin, since arctan(f_c / f_p2) = 30° when f_c = f_p2 / √3.
Third, choose the target GBW from the closed-loop application. For a unity-gain closed-loop amplifier, GBW equals f_c directly. For a closed-loop gain of A_CL, GBW = A_CL · f_c. Then compute:
Cc = gm / (2π · GBW)
This is the starting value. Increase it by 20 to 30 percent for margin against parasitics. Verify that the resulting f_z = gm / (2π · Cc) is at least three times f_c; if not, add the nulling resistor.
Fourth, confirm on the Bode plot of the compensated amplifier that the phase at f_c satisfies −180° + φm ≤ −90° − arctan(f_c / f_p2(new)). If the compensated phase at f_c is, for example, −120 degrees, the phase margin is 60 degrees: satisfactory. If it is −145 degrees, the margin is 35 degrees: insufficient, and Cc must be increased further or the nulling resistor added to recover the lost degrees.
Practical Tradeoffs and What Oversizing Cc Costs
Every picofarad added to Cc reduces the GBW and with it the loop gain available within the audio band. Since total harmonic distortion in a feedback amplifier is approximately equal to the open-loop distortion divided by (1 + loop gain), reducing the loop gain at 20 kHz raises the distortion floor. For a VAS with intrinsic THD of 1% and a loop gain at 20 kHz of 40 dB = 100, the closed-loop THD is 0.01%. Halving the GBW by doubling Cc halves the loop gain at every frequency, raising the closed-loop THD to 0.02%. The phase margin has improved, but the primary performance parameter has worsened by a factor of two.
The slew rate is also directly affected. The slew rate of a Miller-compensated amplifier is set by the maximum current available to charge Cc:
SR = I_tail / Cc
where I_tail is the tail current of the input differential pair. For I_tail = 1 mA and Cc = 100 pF, SR = 10 V/µs. Doubling Cc to 200 pF halves the slew rate to 5 V/µs, which for a full output swing of 40 V places the full-power bandwidth at SR / (2π · V_peak) = 5 × 10⁶ / (2π · 20) ≈ 40 kHz. Large-signal sinusoidal reproduction above 40 kHz becomes slew-rate limited and generates the characteristic triangular-wave distortion of an overdriven bandwidth.
The correct procedure is therefore to find the minimum Cc that satisfies the phase margin criterion, not the largest that fits the PCB footprint. The phase diagram tells the designer exactly where that minimum lies. The second pole frequency on the uncompensated Bode plot is the fixed constraint. The gm of the input stage is a variable that can be adjusted by changing the tail current without touching Cc, since raising I_tail increases gm and raises both GBW and SR simultaneously. Designing first for adequate phase margin, then increasing tail current to recover the GBW and slew rate lost to Cc, is the correct sequence. The phase diagram is the starting document. Everything else follows from reading it correctly.
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