A precision operational amplifier is a remarkably well-engineered device. Its datasheet lists a noise floor measured in nanovolts per root hertz, a distortion figure that struggles to reach a measurable threshold, and a power supply rejection ratio that, at DC, can exceed 100 dB. The manufacturer tested every one of those parameters carefully, on a board designed by engineers who spent considerable effort isolating every variable. That board is not the one being designed. The board being designed has the bypass capacitor grounded at a convenient point, and that point is very likely wrong.
The consequence of this single placement decision, taken in the time it takes to route a trace to the nearest ground via, is the injection of a half-wave rectified distortion current directly into the signal reference node. The op-amp's internal performance becomes irrelevant. The board itself adds an error that the amplifier cannot see, cannot reject, and cannot correct. Understanding why requires looking at what actually flows through a bypass capacitor and where that current goes.
What Flows Through a Bypass Capacitor and Why It Is Not Clean
A bypass capacitor placed between a supply rail and ground is not a passive component during amplifier operation. It is an active current path. At any moment when the op-amp's output stage draws a transient current, whether from a load step, a high-frequency signal swing, or an internal switching event, the power supply cannot respond instantaneously due to the series inductance and resistance of the supply trace. The bypass capacitor fills the gap, delivering the required charge from its stored energy and then recharging from the supply rail once the demand subsides.
The current that flows through the bypass capacitor during this recharge cycle is not a clean sinusoid. The currents flowing in op-amp supply terminals, and therefore through the bypass capacitors, may be distorted because they represent only half a sine wave. This is the same half-wave rectification principle seen in Class AB power stages: the positive supply capacitor delivers and receives charge only during the positive half-cycle of the output signal, and the negative supply capacitor only during the negative. Each capacitor's recharge current is therefore a half-wave rectified version of the load current, rich in even harmonics and a DC component, as described by its Fourier expansion:
i_recharge(t) = I_p/π + (I_p/2)·sin(ωt) − (2I_p/3π)·cos(2ωt) − (2I_p/15π)·cos(4ωt) − ...
where I_p is the peak current drawn by the output stage. The fundamental at ω and its even harmonics at 2ω, 4ω, and beyond are all present, all flowing through the bypass capacitor's ground lead with every audio cycle. If that ground lead connects to a node shared by the signal path, these harmonic currents flow through the parasitic impedance of the common ground trace and generate an error voltage. This error voltage is not supply noise in the ordinary sense. It is correlated with the output signal, which makes it a distortion product indistinguishable from the op-amp's own nonlinearity.
The Node Topology and Where the Error Enters the Signal
The ground network of a practical op-amp circuit contains several nodes that are schematically labeled as ground but are physically separated by the finite impedance of copper traces. Consider an inverting amplifier: the input signal reference is the ground terminal of the source and the lower end of the input resistor. The inverting input of the op-amp connects to the junction of the feedback resistor and the input resistor. The output sees the load and the upper end of the feedback resistor. These nodes are connected to a common ground reference, but in the physical board they are connected through traces, and those traces carry impedance.
Call these nodes A, B, and C: node A is the input signal ground reference, node B is the junction at the inverting input, and node C is the output ground reference. A distorted current flowing into node A directly affects the ground reference of the input signal, summing in an error at the non-inverting input. A ground current injected into node B serves as a direct input to the amplifier stage, added to the inverting input terminal with gain applied to the result. A ground current flowing into node C sums an error with the output voltage, though this node is less vulnerable because the error is not amplified by the circuit gain.
The bypass capacitor's ground pin connects to one of these nodes or to a trace that passes through them on the way to a more remote ground plane connection. In either case, the bypass capacitor's recharge current flows through the parasitic impedance between the ground connection point and the true signal reference. If a ground trace has parasitic resistance R_g and carries a ground distortion current I_g, the reference shift at the input is:
ΔV_node = I_g · Z_g
where Z_g = R_g + jωL_g is the complex impedance of the ground trace at frequency ω. At DC and very low frequencies, Z_g is dominated by R_g alone: for a 10 mm trace of 0.5 mm width in 35 µm copper, the resistance is approximately 5 milliohms. At 20 kHz, the inductive component ωL_g of a 10 mm trace adds roughly 0.1 milliohms. Both are tiny numbers. But the current I_g, being a recharge pulse drawn at the peak of each signal cycle, can be tens of milliamperes even for a small precision op-amp driving a 600-ohm load. The resulting ΔV_node can be several tens of microvolts, which in a circuit with input-referred noise of a few nanovolts per root hertz represents a distortion contribution several orders of magnitude above the device's intrinsic performance floor.
The PSRR Limitation and Why It Does Not Rescue a Bad Layout
A natural counterargument is that the op-amp's power supply rejection ratio should suppress any supply-side contamination. At DC, PSRR for a quality op-amp such as the OPA2134 or AD797 exceeds 100 dB; a 1 mV supply disturbance produces only 10 nV at the output. If the recharge current modulates the supply rail rather than the signal ground, the PSRR would reduce it to irrelevance.
The problem is that the PSRR applies to signals arriving at the supply pins of the IC. It does not apply to signals arriving at the signal input pins. When the bypass capacitor's ground connects to node A or node B, the recharge current generates an error voltage at those nodes directly, not at the supply pin. The op-amp has no mechanism to reject a signal that appears on its own input terminals; it amplifies it. The PSRR rolls off with frequency at approximately 20 dB per decade above the dominant pole, which for most precision op-amps falls between a few hertz and a few hundred hertz. At 10 kHz, a typical PSRR of 100 dB at DC may have fallen to 60 dB or lower. At 100 kHz, it may be 40 dB. Any recharge current that couples into the supply pin rather than the signal ground is at least partially attenuated by PSRR, diminishing at 20 dB per decade. Any recharge current that couples directly into the signal ground enters the signal path without attenuation. The PSRR is irrelevant to the mechanism that matters most.
Identifying the Correct Ground Connection Point
The safe connection point for a bypass capacitor's ground terminal is the node designated G: a point whose voltage variation affects all sensitive signal nodes equally, so that any variation at G appears as a common-mode shift that the differential input of the op-amp rejects, rather than as a differential signal that it amplifies.
In practice, node G is the point where the input signal ground, the output signal ground, and the lower ends of the feedback resistors all meet, before any trace that carries recharge current. The bypass capacitor's ground lead should connect to this node, or to the ground plane at a point that is downstream of it from the perspective of the recharge current path. This way, the recharge current does not flow through any trace that connects to a sensitive signal node. Even if there is additional parasitic impedance between node G and the main ground plane, variations in voltage at G affect all the critical nodes in the same way. A common-mode voltage shift of any magnitude at node G does not appear at the op-amp's differential input and does not contribute to the output error.
The principle is simple: the trace from the input ground terminal to the ground side of the input resistor should be a clear path with no connections to contaminating sources of current along the way. This input ground trace can join a larger ground plane or connection where they meet at node G, but it must not share any portion of its path with the recharge current of the bypass capacitors.
Star Ground Topology as the Physical Implementation
The correct layout realizes this principle as a star ground architecture. All bypass capacitors for a given op-amp connect their ground terminals to a single, local pad. That pad connects to the ground plane at one point, physically close to the IC. The signal input ground reference connects to the ground plane at a separate via that is also close to the IC but does not share a trace with the bypass capacitor ground. In many applications, it is vitally important that all power-supply bypass capacitors and any external compensation capacitors be grounded at a common point on the ground plane, centrally located close to the IC, providing a star ground connection that keeps the inductance of each capacitor's ground line closely matched to that of the others.
With surface-mount components, a practical approach is to create a small copper pad beneath the IC that all local bypass capacitors share for their ground connection, connected to the main ground plane through a single via of minimum length. The via inductance of a standard 0.3 mm via is approximately 0.3 to 0.5 nH per millimeter of via length. Two vias in parallel halve this value. Using two or three vias to connect the bypass ground pad to the plane reduces the inductance of the recharge path, allowing the capacitor to replenish more effectively at high frequencies and reducing the peak recharge current pulse amplitude, which in turn reduces the voltage error at the signal node.
Every capacitor between a supply rail and ground carries the risk of injecting rail noise into the ground if connected at the wrong node. Douglas Self's formulation of this is unambiguous: it is not necessary, and often not desirable, to have two capacitors going to ground. An alternative connection strategy places the bypass capacitor directly between the positive and negative supply pins of a dual-supply op-amp, bypassing the supply differential without routing any recharge current through the signal ground at all. This approach, which avoids the ground path entirely, is viable when the op-amp's PSRR is adequate to handle the resulting common-mode supply variation. For the most demanding precision applications, it does not replace proper star grounding but can supplement it.
Daisy-Chain Ground as the Primary Failure Mode
The failure mode this article addresses is not exotic. It is the default outcome of the most natural layout habit: connecting bypass capacitors to the nearest available ground via, which in most board layouts falls somewhere along the trace from the supply pin to the ground plane, or onto the ground plane at a location that requires the recharge current to traverse the same copper region as the signal return.
A very typical problem occurs when the same grounding point is used for both high- and low-level signals. An extreme case is where a low-level signal component is tied to the same grounding point as a power-supply filter capacitor. The high currents flowing in the capacitor modulate the low-level signal and introduce power-supply harmonics into the signal path. In a daisy-chain ground layout, each stage's bypass capacitor connects to the ground trace at a point between the previous stage's capacitor connection and the next, creating a chain of recharge current contributions that all flow through the same impedance. Each stage downstream sees the accumulated voltage error of all upstream recharge pulses. In a multi-stage precision signal chain, this accumulation can raise the effective noise floor by 20 dB or more compared to a properly star-grounded layout of identical components.
What the Measurement Reveals
The distortion signature of misplaced bypass capacitor grounding is distinctive. It appears as a second-harmonic component that rises with output level and frequency, because the recharge current amplitude scales with I_p and its harmonic content scales with frequency. An op-amp measuring THD+N below 0.001% with a resistive load and no external ground contamination may measure 0.01% or worse when the bypass capacitors are grounded at a point shared with the signal reference and the output current is significant. The improvement achieved by correcting the ground connection is proportional to the ratio of the recharge current amplitude to the signal current in the ground path, which can exceed 20 dB in circuits where the output drives low-impedance loads or where multiple stages share a common ground trace.
The precision op-amp did not change. The circuit topology did not change. The supply voltage did not change. Only the location of one ground via changed, moving the bypass capacitor ground connection from a node shared with the input signal reference to a dedicated node that carries no signal current. That relocation, measured in millimeters on the board, determines whether the amplifier performs to its datasheet specification or underperforms by a factor of ten.
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